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CMOS Mini Mold Package Highly Accurate : 2% Built-In Delay Circuit 1ms ~ 50ms 50ms ~ 200ms 80ms ~ 400ms Low Power Consumption : 1.0A (TYP.) [VIN = 2.0V]
APPLICATIONS
Microprocessor reset circuitry Memory battery back-up circuits Power-on reset circuits Power failure detection System battery life and charge voltage monitors Delay circuitry
GENERAL DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate temperature drift. Both CMOS and N-channel open drain output configurations are available. Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible. with minimal
FEATURES
Highly Accurate : 2% Low Power Consumption : 1.0A(TYP.)[ VIN=2.0V ] : 1.6V ~ 6.0V in 100mV increments Detect Voltage Range Operating Voltage Range : 0.7V ~ 10.0V Detect Voltage Temperature Characteristics :100ppm/(TYP.) Built-In Delay Circuit : 1ms ~ 50ms 50ms ~ 200ms 80ms ~ 400ms Output Configuration : N-channel open drain or CMOS Ultra Small Packages : SOT-23 (150mW) mini-mold : SOT-89 (500mW) mini-power mold : TO-92 (300mW) * No parts are available with an accuracy of 1%
TYPICAL APPLICATION CIRCUITS
TYPICAL PERFORMANCE CHARACTERISTICS
Ambient Temperature:Ta()
XC61F ETR0202_001.doc
117
XC61F Series
PIN CONFIGURATION
PIN ASSIGNMENT
PIN NUMBER SOT-23 3 2 1 SOT-89 2 3 1 TO-92 (T) 2 3 1 TO-92 (L) 1 2 3 PIN NAME VIN VSS VOUT FUNCTION Supply Voltage Input Ground Output
PRODUCT CLASSIFICATION
Ordering Information
XC61F DESIGNATOR DESCRIPTION Output Configuration Detect Voltage SYMBOL C N 16 ~ 60 1 Output Delay Detect Accuracy 4 5 2 M Package P T L R Device Orientation L H B DESCRIPTION : CMOS output : N-ch open drain output : e.g. 2.5V 2 , 5 : e.g. 3.8V 3, 8 : 50ms ~ 200ms : 80ms ~ 400ms : 1ms ~ 50ms : Within 2.0% : SOT-23 : SOT-89 : TO-92 (Standard) : TO-92 (Custom pin configuration) : Embossed tape, standard feed : Embossed tape, reverse feed : Paper type (TO-92) : Bag (TO-92)
118
XC61F
Series
PACKAGING INFORMATION
SOT-23 SOT-89
TO-92
119
XC61F Series
MARKING RULE
SOT-23, SOT-89
3
1
2
1
2
3
Represents integer of detect voltage and output configuration CMOS output (XC61FC series) MARK CONFIGURATION VOLTAGE (V) A CMOS 0.x B CMOS 1.x C CMOS 2.x D CMOS 3.x E CMOS 4.x F CMOS 5.x H CMOS 6.x N-channel open drain (XC61FN series) MARK CONFIGURATION VOLTAGE (V) K N-ch 0.x L N-ch 1.x M N-ch 2.x N N-ch 3.x P N-ch 4.x R N-ch 5.x S N-ch 6.x Represents decimal number of detect voltage MARK VOLTAGE (V) MARK 0 x.0 5 1 x.1 6 2 x.2 7 3 x.3 8 4 x.4 9 Represents delay time VOLTAGE (V) 5 6 7 VOLTAGE (V) x.5 x.6 x.7 x.8 x.9

DELAY TIME 50 ~ 200ms 80 ~ 400ms 1 ~ 50ms
Represents assembly lot number (Based on internal standards)
TO-92
Represents output configuration MARK C N , Represents detect voltage MARK 3 5 Represents delay time MARK 1 4 5 Represents detect voltage accuracy MARK 2
OUTPUT CONFIGURATION CMOS N-ch
3 0
VOLTAGE (V) 3.3 5.0 DELAY TIME 50ms ~ 200ms 80ms ~ 400ms 1ms ~ 50ms DETECT VOLTAGE ACCURACY Within +2%
Represents a least significant digit of the production year (ex.) MARK PRODUCTION YEAR 3 2003 4 2004 Represents production lot number 0 to 9, A to Z repeated (G, I, J, O, Q, W expected)
120
XC61F
Series
BLOCK DIAGRAMS
(1) CMOS output (2) N-channel open drain output
ABSOLUTE MAXIMUM RATINGS
PARAMETER Input Voltage Output Current CMOS Output Voltage N-ch open drain SOT-23 Power Dissipation SOT-89 TO-92 Operating Temperature Range Storage Temperature Range SYMBOL VIN IOUT VOUT RATINGS 12.0 50 VSS -0.3 ~ VIN + 0.3 VSS -0.3 ~ 9 150 500 300 -30+85 -40+125
Ta = 25 UNITS V mA V
Pd Topr Tstg
mW
ELECTRICAL CHARACTERISTICS
PARAMETER Detect Voltage Hysteresis Range SYMBOL VDF VHYS VIN = 1.5V VIN = 2.0V VIN = 3.0V VIN = 4.0V VIN = 5.0V VDF= 1.6V to 6.0V VIN = 1.0V VIN = 2.0V N-ch VDF =0.5V VIN = 3.0V VIN = 4.0V VIN = 5.0V CMOS, P-ch VDF=2.1V VIN = 8.0V CONDITIONS MIN. VDF(T) x 0.98 VDF x 0.02 0.7 VIN changes from 0.6V to 10V 50 TYP. VDF(T) VDF x 0.05 0.9 1.0 1.3 1.6 2.0 2.2 7.7 10.1 11.5 13.0 -10.0 100 -
Ta=25
MAX. VDF(T) x 1.02 VDF x 0.08 2.6 3.0 3.4 3.8 4.2 10.0 200 UNITS V V
Supply Current
ISS
A
Operating Voltage
VIN
V
Output Current
IOUT
mA
Detect Voltage Temperature Characteristics Transient Delay Time (VDR VOUT inversion)
VDF Topr VDF TDLY
ppm/ ms
VDF (T): Setting detect voltage value Release Voltage: VDR = VDF + VHYS * Transient Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available. Note: The power consumption during power-start to output being stable (release operation) is 2A greater than it is after that period (completion of release operation) because of delay circuit through current.
121
XC61F Series
OPERATIONAL EXPLANATION
CMOS output
When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the input at VIN. Note that high impedance exists at VOUT with the N-channel open drain configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage. When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-channel open drain configurations. When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up voltage. When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level. Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.

Notes: 1. The difference between VDR and VDF represents the hysteresis range. 2. Propagation delay time (tDLY) represents the time it takes for VIN to appear at VOUT once the said voltage has exceeded the VDR level.
Timing Chart
122
XC61F
Series
DIRECTIONS FOR USE
Notes on Use
1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded. 2. When a resistor is connected between the VIN pin and the input with CMOS output configurations, oscillation may occur as a result of voltage drops at RIN if load current (IOUT) exists. It is therefore recommend that no resistor be added. (refer to Oscillation Description (1) below) 3. When a resistor is connected between the VIN pin and the input with CMOS output configurations, irrespective of N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load current (IOUT) does not exist. (refer to Oscillation Description (2) below) 4. With a resistor connected between the VIN pin and the input, detect and release voltage will rise as a result of the IC's supply current flowing through the VIN pin. 5. If a resistor (RIN) must be used, then please use with as small a level of input impedance as possible in order to control the occurrences of oscillation as described above. Further, please ensure that RIN is less than 10k and that CIN is more than 0.1F (Figure 1). In such cases, detect and release voltages will rise due to voltage drops at RIN brought about by the IC's supply current.
Oscillation Description
(1) Oscillation as a result of output current with the CMOS output configuration: When the voltage applied at IN rises, release operations commence and the detector's output voltage increases. Load current (IOUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located between the input (IN) and the VIN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect operations will commence. Following detect operations, load current flow will cease and since voltage drop at RIN will disappear, the voltage level at the VIN pin will rise and release operations will begin over again. Oscillation may occur with this " release - detect - release " repetition. Further, this condition will also appear via means of a similar mechanism during detect operations. (2) Oscillation as a result of through current: Since the XC61F series are CMOS ICS, through current will flow when the IC's internal circuit switching operates (during release and detect operations). Consequently, oscillation is liable to occur during release voltage operations as a result of output current which is influenced by this through current (Figure 3). Since hysteresis exists during detect operations, oscillation is unlikely to occur.
Figure 1. When using an input resistor
123
XC61F Series
DIRECTIONS FOR USE (Continued)
Oscillation Description (Continued)
124
XC61F
Series
TYPICAL PERFORMANCE CHARACTERISTICS
125
XC61F Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
126
XC61F
Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
127

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